An integrated circuit is typically formed on a substrate (e.g. a semiconductor wafer) by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer, and by the subsequent processing of the layers.
One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate. In addition, planarization may be used to planarize a dielectric layer for lithography.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier head. The exposed surface of the substrate is placed against a rotating polishing pad. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing liquid, such as slurry with abrasive particles, is supplied to the surface of the polishing pad.
During semiconductor processing, it may be important to determine one or more characteristics of the substrate or layers on the substrate. For example, it may be important to know the thickness of a conductive layer during a CMP process, so that the process may be terminated at the correct time. A number of methods may be used to determine substrate characteristics. For example, optical sensors may be used for in-situ monitoring of a substrate during chemical mechanical polishing. Alternately (or in addition), an eddy current sensing system may be used to induce eddy currents in a conductive region on the substrate to determine parameters such as the local thickness of the conductive region.